ChipForge (Tatsu)
SN84The first decentralised chip design project with AI-assisted semiconductor engineering
The world's first decentralized chip design project. Miners compete to design semiconductor circuits that pass automated test suites. In an industry where chip design costs hundreds of millions of dollars, ChipForge is exploring whether decentralized competition can accelerate the process.
// Decentralized chip design, by competition.
ChipForge is a subnet where miners compete to design semiconductor circuits. Each challenge specifies requirements (functionality, constraints, performance targets), miners submit circuit designs, and validators run those designs against automated testcases to score correctness and efficiency.
The simple version: Imagine a competition where engineers design a microchip to meet specific requirements, and an automated judge tests whether each design actually works. The best design wins. ChipForge runs this competition continuously.
Centralized equivalent: Think Cadence or Synopsys design challenges, or DARPA's electronics design contests, but running continuously as an incentivized marketplace rather than one-off events.
How it works:
- Miners receive chip design challenges and submit solutions (circuit designs) that must pass automated testcase suites. Miner emissions percentage is defined in the codebase, and testcases can be auto-downloaded during challenges.
- Validators run submitted designs against comprehensive testcase suites, scoring based on correctness, efficiency, and adherence to design constraints. Results determine weight allocation.
- The problem it solves: Designing a modern chip costs $100-500 million and takes 2-5 years. The design process is dominated by a few EDA (Electronic Design Automation) companies and a handful of chip design firms. This concentration slows innovation.
- The opportunity: The semiconductor industry is worth $600 billion annually. AI-assisted chip design is an emerging field, with Google, NVIDIA, and startups all investing. Even small improvements in design efficiency have enormous value.
- The Bittensor advantage: Open competition means design approaches from diverse backgrounds, including academia, independent engineers, and AI-augmented designers, all competing simultaneously.
- Traction signals: Built by Tatsu Project. 45 commits across 3 contributors. Active challenges with auto-downloadable testcases. 1,193 holders. Momentum score of 59.6 shows growing interest.
Category: Code Generation and Development Tools | Centralized Competitor: Cadence, Synopsys, Google AI Chip Design, NVIDIA NVCell
ChipForge is one of the most speculative subnets in Bittensor, and arguably one of the most interesting. Semiconductor design is a domain where AI is just beginning to show promise (Google's AlphaChip, NVIDIA's NVCell), and decentralized competition could surface novel approaches that corporate R&D misses.
Mechanism:
Challenges are distributed with specifications and constraints. Miners submit designs that are evaluated against automated testcases. The testcase system supports auto-downloading, meaning challenges can be updated mid-competition without requiring miners to manually fetch new criteria.
The codebase is small: 45 commits across 3 contributors, with development concentrated from atkinson-ai. Recent work (March 2026) focused on miner emission percentage adjustments and testcase auto-download improvements. The last substantive commit was in late January 2026.
This is genuinely early-stage. At 15,750 TAO market cap with 1,193 holders, ChipForge is one of the smallest subnets we've covered. The Gini of 0.782 is the highest in our coverage, and HHI of 0.170 confirms extreme concentration. A single large holder exiting could significantly impact the market.
Root proportion of 0.186 shows organic demand exists despite the concentration. Net 7-day inflow of 179 TAO is modest but positive. The momentum score of 59.6 is driven more by narrative ("decentralized chip design" is a compelling concept) than by development velocity or usage metrics.
The critical question is whether the challenge-and-testcase model can produce genuinely useful chip designs. If ChipForge can demonstrate that a miner-submitted design matches or exceeds what a traditional EDA flow produces, even for simple circuits, it would be a significant proof of concept.
- Extreme concentration: Gini of 0.782 and HHI of 0.170 are the highest in our coverage. This is a whale-dominated subnet.
- Development pace: 45 total commits with minimal recent activity. Chip design infrastructure requires substantial engineering investment.
- Domain expertise barrier: Semiconductor design requires deep specialized knowledge. The pool of potential miners is very small compared to other subnet categories.
- Unproven concept: Decentralized chip design has never been done at scale. The feasibility of competitive circuit design through Bittensor incentives remains theoretical.